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PROGRAMMABLE ARRAY LOGIC

sequential programmable logic devices (PLDs)

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PROGRAMMABLE ARRAY LOGIC

The PAL device is a special case of PLA which has a programmable AND array
and a fixed OR array. The basic structure of Rom is same as PLA. It is cheap
compared to PLA as only the AND array is programmable. It is also easy to program
a PAL compared to PLA as only AND must be programmed.
The figure 1 below shows a segment of an unprogrammed PAL. The input buffer
with non inverted and inverted outputs is used, since each PAL must drive many
AND Gates inputs. When the PAL is programmed, the fusible links (F1, F2, F3…F8)
are selectively blown to leave the desired connections to the AND Gate inputs.
Connections to the AND Gate inputs in a PAL are represented by Xs, as shown here:

As an example, we will use the PAL segment of figure 1 to realize the function
I1I2’+I1I2. the Xs indicate that the I1 and I2’ lines are connected to the first AND Gate, and
the I1’ and I2 lines are connected to the other Gate.

Typical combinational PAL have 10 to 20 inputs and from 2 to 10 outputs with 2
to 8 AND gates driving each OR gate. PALs are also available which contain D flip-flops
with inputs driven from the programming array logic. Such PAL provides a convenient
way of realizing sequential networks. Figure 2 below shows a segment of a sequential
PAL. The D flip-flop is driven from the OR gate, which is fed by two AND gates. The
flip-flop output is fed back to the programmable AND array through a buffer. Thus the
AND gate inputs can be connected to A, A’, B, B’, Q, or Q’. The Xs on the diagram
show the realization of the next-state equation.
Q+ = D = A’BQ’ + AB’Q
The flip-flop output is connected to an inverting tristate buffer, which is enabled when
EN = 1

Figure 3 below shows a logic diagram for a typical sequential PAL, the 16R4.
This PAL has an AND gate array with 16 input variables, and it has 4 D flip-flops. Each
flip-flop output goes through a tristate-inverting buffer (output pins 14-17). One input
(pin 11) is used to enable these buffers. The rising edge of a common clock (pin 1) causes
the flip-flops to change the state. Each D flip-flop input is driven from an OR gate, and
each OR gate is fed from 8 AND gates. The AND gate inputs can come from the external
PAL inputs (pins2-9) or from the flip-flop outputs, which are fed back internally. In
addition there are four input/output (i/o) terminals (pins 12,13,18 and 19), which can be
used as either network outputs or as inputs to the AND gates. Thus each AND gate can
have a maximum of 16 inputs (8 external inputs, 4 inputs fed back from the flip-flop

outputs, and 4 inputs from the i/o terminals). When used as an output, each I/O terminal
is driven from an inverting tristate buffer. Each of these buffers is fed from an OR gate
and each OR gate is fed from 7 AND gates. An eighth AND gate is used to enable the
buffer.

Figure 3: logic diagram for 16R4 pal

When the 16R4 PAL is used to realize a sequential network, the I/O terminals are
normally used for the z outputs. Thus, a single 16R4 with no additional logic could
realize a sequential network with up to 8 inputs, 4 outputs, and 16 states. Each next state

equation could contain up to 8 terms, and each output equation could contain up to 7
terms. As an example, we will realize the BCD to Excess-3 code converter using three
flip-flops to store Q1,Q2 and Q3, and the array logic that drives these flip-flops is
programmed to realize D1, D2 and D3, as shown in figure 3 .The Xs on the diagram
indicate the connections to the AND-gate inputs. An X inside an AND gate indicates that
the gate is not used. For D3, three AND gates are used, and the function realized is

D3 = Q1Q2Q3 + X’Q1Q3’ + XQ1’Q2’

The flip-flop outputs are not used externally, so the output buffers are disabled. Since the
Z output comes through the inverting buffer, the array logic must realize

Z’ = (X + Q3)(X’ + Q3’) = XQ3’ + X’Q3

The z output buffer is permanently enabled in this example, so there are no connections
to the AND gate that drives the enable input, in which case the AND gate output is
logic1.
When designing with PALS, we must simplify our logic equations and try to fit them in
one or more PALs. Unlike the more general PLA, the AND terms cannot be shared
among two or more OR gates; therefore, each function to be realized can be simplified by
itself without regard to common terms. For a given type of PAL the number of AND
terms that feed each output OR gate is fixed and limited. If the number of AND terms in
a simplified function is too large, we may be forced to choose a PAL with more OR-gate
inputs and fewer outputs.
Computer aided design programs for PAL s are widely available. Such programs accept
logic equations, truth tables, state graphs, or state tables as inputs and automatically
generate the required fused patterns. These patterns can then be downloaded into a PLD
programmer, which will blow the required, fuses and verify the operation of the PAL.