STATE GRAPHS FOR CONTROL NETWORKS
Serial adder with Accumulator
VHDL CODE for the 16 bit serial adder
Binary Multiplier
VHDL code for 4 X 4 Binary Multiplier
Multiplier Control with Counter
Operation of Multiplier using a Counter
4bit Multiplier Partial Products
State Graph for 2’s Complement Multiplier
Block diagram for Faster Multiplier
VHDL Code Behavioral Model for 2’s Complement Multiplier
Test Bench for Signed Multiplier
Design of the control circuit in a Multiplier using a counter (74163)
Binary Divider
Block diagram for Signed Divider
VHDL Model of 32bit Signed Divider 
Binary Divider
Procedure:
Block Diagram for Parallel Binary Divider
Sequence of functions:
A shift signal (Sh) will shift the dividend one place to the left.
A subtract signal (Su) will subtract the divisor from the 5 leftmost bits in the
dividend register and set the quotient bit (the rightmost bit in the dividend register)
to 1.
If the divisor is greater than the 4 leftmost dividend bits, the comparator output is
C=0; otherwise, C=1.
The control circuit generates the required sequence of shift and subtract signals.
Whenever C=0, subtraction can not occur, so a shift signal is generated and quotient
bit is set to 0.
Whenever C=1, a subtraction signal is generated, and the quotient bit is set to 1.
Example (135 / 13):
Overflow
• As a result of a division operation, If the quotient contains more bits than are
available for storing the quotient, we say that an overflow has occurred.
• It is not necessary to carry out the division if an overflow condition exists.
• An initial comparison of the dividend and divisor determine whether the quotient
will be too large or not.
Detection of Overflow
State Diagram for Divider Control Circuit
Operation of the Divider
• When a start signal (St) occurs, the 8bit dividend and 4bit divisor are loaded into
the appropriate registers
• If C is 1, the quotient would require five or more bits. Since space is only provided
for 4bit quotient, this condition constitutes an overflow, so the divider is stopped
and the overflow indicator is set by the V output.
• Normally, the initial value of C is 0, so a shift will occur first, and the control circuit
will go to state S2.
• Then, if C=1, subtraction occurs. After the subtraction is completed, C will always
be 0, so the next clock pulse will produce a shift.
• This process continues until four shifts have occurred and the control is in state S5.
• Then a final subtraction occurs if necessary, and the control returns to the stop
state. For this example, we will assume that when the start signal (St) occurs, it will
be 1 for one clock time, and then it will remain 0 until the control network is back in
state S0. Therefore, St will always be 0 in states S1through S5.
Question 4.5 (a) Draw the block diagram for divider for unsigned binary number that
divides an 8 bit dividend by a 3 bit divisor to give a 5 bit quotient
(b) Draw state graph for the control circuit, assume that the start signal (st) is
present for 1 clock period.
(c) Write VHDL description of the divider.
(a) Block diagram for divider for unsigned binary number
(b) Refer State Diagram for Divider Control Circuit
(c) VHDL description of the divider:
library ieee;
use ieee.std_logic_1164.all;
entity divider is
port (St, Clk: in std_logic;
dend: in std_logic_vector(7 downto 0);
dsor: in std_logic_vector(2 downto 0);
v: out std_logic;
qent: out std_logic_vector(4 downto 0));
end divider;
architecture beh of divider is
signal C, Sh, su, Ld: std_logic;
signal DendR: std_logic_vector(8 downto 0);
signal DsorR: std_logic_vector(2 downto 0);
signal Sub: std_logic_vector(4 downto 0);
signal State, nxState: integer range 0 to 6;
begin
Sub <= Add4 (DendR(8 downto 5), not(‘0’ & DsorR), ‘1’);
C<=sub(4);
Qent<=DendR(4 downto 0);
Process (state, st, C)
Begin
V<= ‘0’; Sh<= ‘0’; Su<=’0’; Ld<=’0’;
Case state is
When 0=> if (St=’1’) then Ld<=’1’; nxState<=’1’;
Else nxstate<=’0’; end if;
When 1=> if(C=’1’) then V<=’1’; nxstate<=’0’;
Else Sh<=’1’; nxState<=2; end if;
When 2345 => if (C=’1’) then Su<=’1’; nxstate<=State;
Else Sh<=’1’; nxstate<=state + 1; end if;
When 6 => if (C=’1’) then Su<=’1’; end if;
nxState<=’0’;
end case;
end process;
process (Clk)
begin
if (Clk=’1’ and Clk’event) then
state<=nxState;
if (Ld=’1’) then
DendR<=’0’ & dend;
DsorR<=dsor; end if;
If (Sh=’1’) then
DendR<= DendR (7 downto 0) & ‘0’; end if;
If (Su=’1’) then
DendR(8 downto 5) <=sub(3 downto 0);
DendR(0)<=’1’; end if;
End if;
End process;
End divider;

