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VHDL Models for Memories and Busses

6116 static CMOS RAM

Timing Diagrams

Simple VHDL Model for RAM Memory

Testing the RAM Model

VHDL Program acting as a Tester for simple RAM model

Development of VHDL Program for a RAM memory model with timing

Complete VHDL Program for the memory model with timing (OE_b=0)

VHDL Code for Testing the RAM timing Model

Microprocessor Bus Interface

VHDL Model for 486 bus interface unit

Timing Specification Of 486 Processor Bus

Interfacing Memory To a Microprocessor Bus

Signal Paths for Memory Read

SM Chart for Memory Controller

VHDL Models for Memories and Busses

In this unit the following topics are described:
• the operation of a static RAM memory
• developing VHDL models to represent the operation and timing characteristics of the
• the operation of a microprocessor bus interface and developing a VHDL timing model for
• Design of an interface between memory and the microprocessor bus.
• Use the developed VHDL memory and bus models to verify that the timing specifications
for the memory and bus interface have been satisfied.

Static RAM Memory

Fig . 1 Block Diagram of Static RAM

RAM stands for random access memory, which means that any word memory can be
accessed in the same amount of the time as any other word. Figure 1 shows the block diagram of
a static RAM with n address lines, M data lines, and three control lines. This memory can store a
total of words, each m bits wide. The data lines are bi-directional in order to reduce the
required number of pins and the package size of the memory chip. When reading from the RAM,
the data lines are output; when writing to the RAM, the data lines serve as inputs. The three
control lines function as follows:
When asserted low, chip select selects the memory chip so that memory read and write
operations are possible.

When asserted low, output enable enables the memory output onto an external bus.
When asserted low, write enable allows data to be written to the RAM.
(We say that a signal is asserted when it is in its active state. An active-low signal is
asserted when it is low, and an active-high signal is asserted when it is high.)

The RAM contains address decoders and a memory array. The address inputs to the
RAM are decoded to select cells within the RAM. Figure 2 shows the functional equivalent of a
static RAM cell that stores one bit of data. The cell contains a transparent D latch, which stores
the data. When is asserted low and is high, G = 0, the cell is in the read mode, and Data
Out = Q. When is asserted low and is high, G = 1 and data can enter the transparent
latch. When either and goes high, the data is stored in the latch. When is high, Data
Out is high-Z.