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Concept of Interrupt

Sequence of events

More Details on Interrupts


Concept of Interrupt

A computer has only two ways to determine the conditions that exist in internal and external
circuits. One method uses software instructions that jump to subroutines on the states of flags
and port pins. The second method responds to hardware signals, called interrupts that force
the program to call a subroutine. Most applications of microcontroller involve responding to
events quickly enough to control the environment that generates the events termed real-time
Interrupts may be generated by internal chip operation or provided by external sources. Any
interrupt can cause the 8051 to perform a hardware call to an interrupt-handling subroutine
that is located at a predetermined absolute address in program memory.
The 8051 has five interrupts of which three are internally generated namely:

1. Timer 0 overflow: This is indicated by TF0 in TCON, being set
2. Timer 1 overflow: This is indicated by TF1 in TCON, being set
3. Serial port interrupts (RI and TI): Whenever a data byte is received, an interrupt
bit, RI is set to 1 in SCON register. When a data byte is transmitted an interrupt bit TI,
is set in SCON. They are ORed together to provide a single interrupt to the processor.
These flags must be reset by software instruction to enable the next data
communication operation.
Two interrupts are triggered by external signals provided by circuitry that is connected to pins
INTO and INT1 (P3.2 and P3.3).

1. External signal at pin INTO (P3.2):

When a high-to-low edge signal is received on
P3.2, the external interrupt 0 edge flag IE0 (TCON.1) is set. This flag is cleared when
the processor branches to the subroutine. When the external interrupt signal control
bit IT0 (TCON.0) is set to 1 (by program) then interrupt is triggered by falling edge
signal. If IT0 is 0, a low-level signal in INTO triggers the interrupt.

2. External signal at pin INT1 (P3.3):

Flags IE1 (TCON.3) and IT1 (TCON.2) are
similar to IE0 and IT0 in function.
Each of these interrupts has an address associated where the routine is to be written called as
interrupt service routine addresses. The addresses are listed below: