ELECTRICAL MACHINES - I
POWER PLANT ENGINEERING
LINEAR INTEGRATED CIRCUITS AND
DIGITAL LOGIC CIRCUITS
MODERN CONTROL SYSTEMS
POWER SYSTEM ANALYSIS
ELECTRICAL MACHINE DESIGN
RENEWABLE ENERGY SOURCES
ELECTRIC ENERGY GENERATION
CONSERVATION AND UTILIZATION
DIGITAL LOGIC CIRCUITS
PART-A (2 MARKS)
1. Define binary logic?
2. What are the basic digital logic gates?
3. What is a Logic gate?
4. Give the classification of logic families.
5. Which gates are called as the universal gates? What are its advantages?
6. Classify the logic family by operation?
7. Mention the important characteristics of digital IC’s?
8. Define Fan-out?
9. Define power dissipation?
10. What is propagation delay?
11. Define noise margin?
12. Define fan in?
13. What is Operating temperature?
14. What is High Threshold Logic?
15. Define combinational logic
16. Explain the design procedure for combinational circuits
17. Define Half adder and full adder
18. Define Decoder?
19. What is binary decoder?
20. Define Encoder?
21. What is priority Encoder?
22. Define multiplexer?
23. What do you mean by comparator
1. Obtain the minimum sop using QUINE- McCLUSKY method and verify using K-map
F=m0+m2+m4+m8+m9+m10+m11+m12+m13 (16 marks)
2. Reduce the following using tabulation method. (16 marks)
3. Reduce the Boolean function using k-map technique and implement using gates f
(w, x, y, z)= _m (0,1,4,8,9,10) which has the don’t cares condition d (w, x, y, z)= _m
(2,11). (16 marks)
4. a) Design an 8421 to gray code converter. (8 marks)
b) Implement the Boolean function using 8:1 mux. (8 marks)
F (A, B, C, D) =A’BD’+ACD+B’CD+A’C’D.
5. Design A Full Adder And A Full Subtractor. (16 marks)
6. A combinational circuit is defined by the following three Boolean functions
F1 = x’y’z’+xz
Design the circuit with a decoder and external gates. (16 marks)
7. Simplify the following Boolean function by using Tabulation method
F (w, x, y, z) =_m (0, 1, 2, 8, 10, 11, 14, 15) (16 marks)
8. Simplify the following Boolean functions by using K’Map in SOP & POS.
F (w, x, y, z) = _m (1, 3, 4, 6, 9, 11, 12, 14) (16 marks)
9. a) Design a 2 bit magnitude comparator. (8 marks)
b) Explain the operation of 4 to 10 decoder. (8 marks)
10. a) Design a 4-bit binary to excess-3 converter using the unused combinations of
the code as don’t care conditions. Represent the converter using logic diagram.
PART-A (2 MARKS)
1. What are the classification of sequential circuits?
2. Define Flip flop.
3. What are the different types of flip-flop?
4. What is the operation of D flip-flop?
5. What is the operation of JK flip-flop?
6. What is the operation of T flip-flop?
7. Define race around condition.
8. What is edge-triggered flip-flop?
9. What is a master-slave flip-flop?
10. Define rise time.
11. Define fall time.
12. Define skew and clock skew.
13. Define setup time.
14. Define hold time.
15. Define propagation delay.
16. Define registers.
17. Define sequential circuit?
18. Give the comparison between combinational circuits and sequential circuits.
19. What do you mean by present state?
20. What do you mean by next state?
21. State the types of sequential circuits?
22. Define synchronous sequential circuit
1. A sequential circuit has 2D ff’s A and B an input x and output y is specified by the following
next state and output equations.
A (t+1)= Ax + Bx
B (t+1)= A’x
Y= (A+B) x’
(i) Draw the logic diagram of the circuit.
(ii) Derive the state table.
(iii) Derive the state diagram. (16 marks)
2. Design a mod-10 synchronous counter using Jk ff. write excitation table and state table.
3. a) Write the excitation tables of SR, JK, D, and T Flip flops (8 marks)
b) Realize D and T flip flops using Jk flip flops (8 marks)
4. Design a sequential circuit using JK flip-flop for the following state table [use state diagram]
5. Design a counter with the following repeated binary sequence:0, 1, 2, 3, 4, 5, 6.use JK Flipflop.
6. Derive the state table and state diagram of the sequential circuit shown in figure.
PART-A (2 MARKS)
1. Define Asynchronous sequential circuit?
2. Give the comparison between synchronous & Asynchronous sequential circuits?
3. The following wave forms are applied to the inputs of SR latch. Determine the Q waveform
Assume initially Q = 1
4. What is race around condition?
5. Give the comparison between synchronous & Asynchronous counters.
6. The t pd for each flip-flop is 50 ns. Determine the maximum operating frequency for
MOD - 32 ripple counter
7. What are secondary variables?
8. What are excitation variables?
9. What is fundamental mode sequential circuit?
10. What are pulse mode circuit?
11. What are the significance of state assignment?
12. When do race condition occur?
13. What is non critical race?
14. What is critical race?
15. When does a cycle occur?
16. What are the different techniques used in state assignment?
17. What are the steps for the design of asynchronous sequential circuit?
18. What is hazard?
19. What is static 1 hazard?
20. What is static 0 hazard?
21. What is dynamic hazard?
22. What is the cause for essential hazards?
23. What is flow table?
24. What is primitive flow chart?
25. What is combinational circuit?
26. Define merger graph.
27. Define closed covering.
28. Define state table.
29. Define total state
30. What are the steps for the design of asynchronous sequential circuit?
31. Define primitive flow table.
32. What are the types of asynchronous circuits?
33. Give the comparison between state Assignment Synchronous circuit and state
assignment asynchronous circuit.
34. What are races?
35. Define non critical race.
36. Define critical race?
37. What is a cycle?
38. Write a short note on fundamental mode asynchronous circuit.
39. Write a short note on pulse mode circuit.
40. Define secondary variables.
41. Define flow table in asynchronous sequential circuit.
42. What is fundamental mode.
43. Write short note on shared row state assignment.
44. Write short note on one hot state assignment.
45. A pulse mode asynchronous machine has two inputs. If produces an output
whenever two consecutive pulses occur on one input line only. The output remains at 1
until a pulse has occurred on the other input line. Write down the state table for the machine.
1. Design an asynchronous sequential circuit that has 2 inputs x2 and x1, and one output z.
the output is to remain 0 as long as an X1 is 0. The first change in x2 that occurs while x1 is
1 will cause z to be 1. Z is to remain 1 until x1 returns to 0. Construct a state diagram and
flow table. Determine the output equations. (16 Marks)
2. Design a circuit with inputs A and B to give an output z=1 when AB=11 but only if A
becomes 1 before B, by drawing total state diagram, primitive flow table and output map in
which transient state is included. (16 Marks)
3. Obtain the primitive flow table for an asynchronous circuit that has 2 input’s x, y and
output z. an output z=1, is to occur only during the input state xy=01 and then if and
only if the input state xy=01 is preceded by the input sequence xy=01, 00, 10, 00, 10,
00 (16 Marks)
4. Design a circuit with input a and b to give an output z=1 when AB =11 but only if
A becomes 1 before B, by drawing total state diagram, primitive flow table and output
map in which transient state is included. (16 Marks)
5. Design a asynchronous sequential circuit with 2 inputs T and C. The output attains
a value of 1 when T = 1 & c moves from 1 to 0. Otherwise the output is 0. (16 Marks)
6. Design an Asynchronous sequential circuit using SR latch with two inputs A and B
and one output y. B is the control input which, when equal to 1, transfers the input A to
output y. when B is 0, the output does not change, for any change in input. (16 Marks)
7. a. Explain the difference between synchronous and asynchronous sequential circuits.
b. Derive the transition table for the asynchronous sequential circuit shown below.
Determine the sequence of internal states Y1Y2 for the following sequence of inputs
x1x2 : 00,10,11,01,11,10,00. (10 Marks)
8. Derive the transition table and logic diagram for an asynchronous sequential circuit with the
help of the following flow table. (16 Marks
PART-A (2 MARKS)
1. Mention the classification of saturated bipolar logic families.
2. Explain ROM
3. What are the types of TTL logic?
4. Define address and word.
5. What is programmable logic array? How it differs from ROM?
6. Explain EPROM.
7. Give the classification of PLD’s.
8. Define PROM.
9. Define PLA
10. Define PAL
11. Why was PAL developed ?
12. Why the input variables to a PAL are buffered
13. What does PAL 10L8 specify ?
14. Give the comparison between PROM and PLA.
15. What is mask - programmable?
16. What is field programmable logic array?
17. State advantages and disadvantages of TTL
1. a) Explain in detail about PLA with a specific example. (8 marks)
b) Explain with neat diagrams RAM architecture (8 marks)
2. Implement the following function using PLA.
A (x, y, z) = _m (1, 2, 4, 6)
B (x, y, z) = _m (0, 1, 6, 7)
C (x, y, z) = _m (2, 6) (16 marks)
3. Implement the following function using PAL.
W (A, B, C, D) = _m (2, 12, 13)
X (A, B, C, D) = _m (7, 8, 9, 10, 11, 12, 13, 14, 15)
Y (A, B, C, D) = _m (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
Z (A, B, C, D) = _m (1, 2, 8, 12, 13) (16 marks)
4. Discuss on the concept of working and applications of following memories.
iii) PLA. (16 marks)
5. i) A combinational circuit is defined by the functions.
F1 (a, b, c) = _ m (3, 5, 6, 7)
F2 (a, b, c) = _ m (0, 2, 4, 7) implement the circuit with a PLA. (8 marks)
ii) Write short notes on semiconductor memories (8 marks)
6. a) compare the various digital logic families. (8 marks)
b) Write notes on FPGA. (8 marks)
7. Write notes on the characteristics and implementation of the following digital logic families.
ii) TTL (16 marks)
PART-A (2 MARKS)
1. What do the acronyms VHDL and VHLSI stand for?
2. What are the different types of modeling VHDL?
3. What is packages and what is the use of these packages
4. What is variable class ,give example for variable
5. Name two subprograms and give the difference between these two.
6. What is subprogram Overloading
7. write the VHDL coding for a sequential statement (d-flipflop )
8. What are the different kinds of the test bench?
9. What is Moore FSM
10. Write the testbench for and gate
1) Write a HDL code for state machine to BCD to ex–3 codes Converter. (16 marks)
2) Write a behavioral VHDL description of the 4 bit counter. (16 marks)
3) (I) Write VHDL code for a full sub tractor using logic Equation (8 Marks)
(II) Write a VHDL description of an S-R latch using a process (8 Marks)
4) Write a HDL code for 8:1 MUX using behavioral model (16 marks)
5) Write the HDL description of the circuit specified by the Following Boolean equations
S = xy ‘+ x’ y
6) (I) Write an HDL data flow description of a 4 bit adder subtractor of Unsigned numbers use
the conditional operator (16 marks)
(II) Write the HDL gate level description of the priority encoder (16 marks)